ROCKWELL AADvance Controller T9110 处理器模块
The T9110 processor module is the central processing unit of an AADvance controller. The processor module carries out the following critical process and safety controller tasks: Execution of the AADvance Safety Kernel to solve application logic
Interfacing with the controller I/O modules, reading and processing input data and writing output data
Communication with other processor modules, both locally and across the control network
Initiation of periodic diagnostics for the controller
Communication with other systems such as HMIs
Message encapsulation and verification for secure channel communication to other nodes
The processor module is galvanically isolated from external power supplies and data links so that any faults developed in the field cannot cause the module to fail. The module will continue to operate in the event of failure of one of its dual redundant 24V dc power supplies. The module incorporates under- and over-voltage protection for its internal power supplies, which provide a 'power valid' signal to the modules own diagnostics microprocessor.
A processor module has two functionally independent, electrically isolated Ethernet ports. Each port is separately configurable for multiple protocols such as Modbus RTU, Open Modbus/TCP and proprietary AADvance protocols, and its data is available to every processor in the controller. T
wo serial communications ports per processor are provided for Modbus RTU slave communications.
These ports are also functionally and electrically isolated from each other. They support RS-485 (4– and 2–wire) communications and can be configured to support asynchronous data rates from 1,200 to 115,200 baud.
The processor periodically initiates internal diagnostic tests which, together with a watchdog circuit, monitor the processor internal performance. If the tests detect a serious fault, the processor module will shut down. A controller can use one, two or three processor modules. Using two or three processor modules provides a fault tolerant processor architecture.
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